/***************************************************************************//**
* \file cyhal_triggers_explorer.c
*
* \brief
* Explorer family HAL triggers header
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

#include "cy_device_headers.h"
#include "cyhal_hw_types.h"

#ifdef CY_DEVICE_EXPLORER
#include "triggers/cyhal_triggers_explorer.h"

const uint16_t cyhal_sources_per_mux[7] =
{
    62, 3, 21, 73, 3, 65, 8,
};

const bool cyhal_is_mux_1to1[7] =
{
    false, false, false, false, false, false, true,
};

const _cyhal_trigger_source_explorer_t cyhal_mux0_sources[62] =
{
    _CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15,
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0,
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1,
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2,
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3,
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4,
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5,
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6,
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7,
    _CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0,
    _CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1,
    _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0,
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1,
    _CYHAL_TRIGGER_TDM_TR_TX_REQ0,
    _CYHAL_TRIGGER_TDM_TR_RX_REQ0,
    _CYHAL_TRIGGER_TDM_TR_TX_REQ1,
    _CYHAL_TRIGGER_TDM_TR_RX_REQ1,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ0,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ1,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ2,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ3,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ4,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ5,
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0,
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1,
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2,
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3,
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4,
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5,
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6,
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7,
    _CYHAL_TRIGGER_I3C_TR_TX_REQ,
    _CYHAL_TRIGGER_I3C_TR_RX_REQ,
    _CYHAL_TRIGGER_MXNNLITE_TR_MXNNLITE,
};

const _cyhal_trigger_source_explorer_t cyhal_mux1_sources[3] =
{
    _CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0,
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1,
};

const _cyhal_trigger_source_explorer_t cyhal_mux2_sources[21] =
{
    _CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
    _CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0,
    _CYHAL_TRIGGER_CANFD_TR_FIFO00,
    _CYHAL_TRIGGER_CANFD_TR_FIFO10,
    _CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1,
    _CYHAL_TRIGGER_CANFD_TR_FIFO01,
    _CYHAL_TRIGGER_CANFD_TR_FIFO11,
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0,
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1,
    _CYHAL_TRIGGER_LPCOMP_DSI_COMP0,
    _CYHAL_TRIGGER_LPCOMP_DSI_COMP1,
    _CYHAL_TRIGGER_TDM_TR_TX_REQ0,
    _CYHAL_TRIGGER_TDM_TR_RX_REQ0,
    _CYHAL_TRIGGER_TDM_TR_TX_REQ1,
    _CYHAL_TRIGGER_TDM_TR_RX_REQ1,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ0,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ1,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ2,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ3,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ4,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ5,
};

const _cyhal_trigger_source_explorer_t cyhal_mux3_sources[73] =
{
    _CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14,
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15,
    _CYHAL_TRIGGER_SCB0_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB1_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB2_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB3_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB4_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB5_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB6_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB7_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB8_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB9_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB10_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB11_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB0_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB1_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB2_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB3_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB4_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB5_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB6_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB7_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB8_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB9_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB10_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB11_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED,
    _CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0,
    _CYHAL_TRIGGER_CANFD_TR_FIFO00,
    _CYHAL_TRIGGER_CANFD_TR_FIFO10,
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0,
    _CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1,
    _CYHAL_TRIGGER_CANFD_TR_FIFO01,
    _CYHAL_TRIGGER_CANFD_TR_FIFO11,
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1,
    _CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0,
    _CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1,
    _CYHAL_TRIGGER_TDM_TR_TX_REQ0,
    _CYHAL_TRIGGER_TDM_TR_RX_REQ0,
    _CYHAL_TRIGGER_TDM_TR_TX_REQ1,
    _CYHAL_TRIGGER_TDM_TR_RX_REQ1,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ0,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ1,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ2,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ3,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ4,
    _CYHAL_TRIGGER_PDM_TR_RX_REQ5,
};

const _cyhal_trigger_source_explorer_t cyhal_mux4_sources[3] =
{
    _CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
    _CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0,
    _CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1,
};

const _cyhal_trigger_source_explorer_t cyhal_mux5_sources[65] =
{
    _CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT00,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT10,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT01,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT11,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT02,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT12,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT03,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT13,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT04,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT14,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT05,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT15,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT06,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT16,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT07,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT17,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0256,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1256,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0257,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1257,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0258,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1258,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0259,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1259,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0260,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1260,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0261,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1261,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0262,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1262,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0263,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1263,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0264,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1264,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0265,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1265,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0266,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1266,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0267,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1267,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0268,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1268,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0269,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1269,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0270,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1270,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0271,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1271,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0272,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1272,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0273,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1273,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0274,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1274,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0275,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1275,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0276,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1276,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0277,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1277,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0278,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1278,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0279,
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1279,
};

const _cyhal_trigger_source_explorer_t cyhal_mux6_sources[8] =
{
    _CYHAL_TRIGGER_SCB0_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB0_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB1_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB1_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB2_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB2_TR_RX_REQ,
    _CYHAL_TRIGGER_SCB3_TR_TX_REQ,
    _CYHAL_TRIGGER_SCB3_TR_RX_REQ,
};

const _cyhal_trigger_source_explorer_t* cyhal_mux_to_sources[7] =
{
    cyhal_mux0_sources,
    cyhal_mux1_sources,
    cyhal_mux2_sources,
    cyhal_mux3_sources,
    cyhal_mux4_sources,
    cyhal_mux5_sources,
    cyhal_mux6_sources,
};

const uint8_t cyhal_dest_to_mux[69] =
{
    2, /* CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK0 */
    2, /* CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK1 */
    1, /* CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN0 */
    1, /* CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN1 */
    3, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 */
    3, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN0 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN1 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN0 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN1 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN2 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN3 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN4 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN5 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN6 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN7 */
    128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN8 */
    128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN9 */
    128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN10 */
    128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN11 */
    128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN12 */
    128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN13 */
    128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN14 */
    128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN15 */
    0, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN0 */
    0, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN1 */
    0, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN2 */
    0, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN3 */
    5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE0 */
    5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE1 */
    5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE2 */
    5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE3 */
    5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE4 */
    5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE5 */
    4, /* CYHAL_TRIGGER_PDM_TR_DBG_FREEZE */
    4, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */
    4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */
    4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 */
    4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 */
    4, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */
    4, /* CYHAL_TRIGGER_TDM_TR_DBG_FREEZE */
};

const uint8_t cyhal_mux_dest_index[69] =
{
    28, /* CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK0 */
    29, /* CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK1 */
    0, /* CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN0 */
    1, /* CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN1 */
    0, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 */
    1, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 */
    8, /* CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN0 */
    9, /* CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN1 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN0 */
    1, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN1 */
    2, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN2 */
    3, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN3 */
    4, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN4 */
    5, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN5 */
    6, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN6 */
    7, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN7 */
    0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN8 */
    1, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN9 */
    2, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN10 */
    3, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN11 */
    4, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN12 */
    5, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN13 */
    6, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN14 */
    7, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN15 */
    10, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN0 */
    11, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN1 */
    12, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN2 */
    13, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN3 */
    0, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE0 */
    1, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE1 */
    2, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE2 */
    3, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE3 */
    4, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE4 */
    5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE5 */
    3, /* CYHAL_TRIGGER_PDM_TR_DBG_FREEZE */
    0, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */
    4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */
    5, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 */
    6, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT */
    0, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */
    1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */
    2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */
    3, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */
    4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */
    5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */
    6, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */
    7, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */
    8, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */
    9, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */
    10, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */
    11, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */
    12, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */
    13, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */
    14, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */
    15, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */
    16, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */
    17, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */
    18, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */
    19, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */
    20, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */
    21, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */
    22, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */
    23, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */
    24, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */
    25, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */
    26, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */
    27, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 */
    1, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */
    2, /* CYHAL_TRIGGER_TDM_TR_DBG_FREEZE */
};

#endif /* CY_DEVICE_EXPLORER */
